The present invention relates generally to digital-to-analog converter circuitry (or device) employing a delta-sigma (.DELTA..SIGMA.) modulator, and more particularly to an improved digital-to-analog converter circuit having a function to calibrate its output offset voltage (i.e., offset adjustment function).
In recent years, there have been employed, in the technical field of digital audio, one-bit digital-to-analog converters (hereinafter, sometimes called DACs) which use a delta-sigma (.DELTA..SIGMA.) modulator to re-quantize multi-bit digital data into one-bit digital data. Generally, delta-sigma modulators are implemented by modifying the design of a conventional delta (.DELTA.) modulator having an input stage provided with an integrator to boost low-frequency components and an output stage provided with a differentiator for cutting-off low-frequency components, and they are known as having the noise-shaping effect that pushes quantization noise toward the high-frequency regions to thereby enhance the S/N ratio in the audio frequency range.
These one-bit DACs with the delta-sigma modulator, however, have the problem that during a silent period, such as a period between difference music pieces, when "zero-value" input data occur in succession after a successive train of digital input data, some of the data left in the integrator would present unstable outputs and even lead to undesirable oscillation, resulting in unwanted noise in the audio frequency range. One typical example of the conventional approaches to avoid such undesirable oscillation in the audio frequency range is to apply oscillation-preventing direct current (D.C.) values to the input stage of the DAC as so-called "D.C. dither". The use of such D.C. dither can convert, into random (white) noise, the residual noise that would occur during successive input of "zero-value" signals.
Also, as an approach to automatically adjust D.C. offset in the DACs, it has been known to cancel the offset value by comparing each DAC's output with a reference potential level during a predetermined calibration period when zero-value input data occur in succession. During normal operation, the offset value determined during the calibration period is retained in a register or the like and fixedly applied to the addition input of the DAC, as disclosed in, for example, Japanese Patent Laid-open Publication No. HEI-4-245717.
However, significant inconveniences would arise where the approach of applying the oscillation-preventing D.C. dither is combined with the approach of automatically adjusting D.C. offset. Namely, because the D.C. dither operate equivalently to the random offset applied to the input stage of the DAC, applying the offset values to the input stage for addition or subtraction as mentioned above would cancel the effect of the D.C. dither in the DAC.